China has demonstrated 7nm production without EUV, stockpiled ninety advanced lithography machines, and invested hundreds of billions to semiconductor self-sufficiency. Yet the gap with TSMC is not closing — it is, in fact, in some critical dimensions, widening. From the very outlook, it appears to be an engineering problem, not a political one.
August 2023 — stripdown of Huawei Mate 60 Pro sent shockwaves through the Western semiconductor and defence establishments. Inside the device was a Kirin 9000s chip — manufactured by SMIC at what appeared to be done by a 7nm processing node. At the time, SMIC was not supposed to be able to do that. Clearly, it appeared to be ahead of its time.
EUV lithography machines, widely considered as prerequisite for sub-10nm production, had been blocked from export to China since 2019. The US intelligence community had apparently missed their mark. Thus, policy circles scrambled. The headlines flashed, declaring that China had made a breakthrough.
Yes, they had.
But the nature of that breakthrough is almost universally misunderstood — and the serious misunderstanding matters for anyone trying to assess where China actually stands, what it can realistically achieve, and what its gap with TSMC actually represents in engineering terms.
Hence, this article attempts to provide that grounded assessment. Given that the semiconductor gap between China and Taiwan is not merely a story about politics and sanctions. It represents a story about expertise, of process engineering, accumulated institutional knowledge, and the sheer compounding nature of manufacturing excellence achieved over time.
What China Actually Did — And What It Cost
The Kirin 9000s chip was real. SMIC's 7nm capability was real. But the method behind — and its implications for scale — is what most of the coverage entirely missed.
To manufacture chips at 7nm, TSMC uses EUV lithography: a process that uses light having 13.5nm wavelength, produced by firing laser pulses at 50,000 tin droplets per second, that in turn produces plasma, and that emits the radiation precise enough to etch features smaller than the size of a virus. A single EUV exposure can draw pattern, printing critical layer of a chip in one pass. In this regard, ASML holds complete monopoly over EUV tools. And China cannot legally obtain them.
SMIC's engineers resorted to solving this differently.
They used DUV immersion lithography — an older generation of the process that operates at 193nm. They combined it with a technique called self-aligned quadruple patterning (SAQP). Where EUV prints a critical layer in one pass, SAQP requires four exposures, with extreme precision and alignment at each step.
A modern 7nm logic chip requires more than 80 lithography steps in total.
With EUV, roughly nine of the most critical steps are handled cleanly in single passes. But, with DUV multi-patterning, those same steps require 34 separate exposures. Each additional exposure introduces alignment error. Each alignment error increases defect density. And defect density directly determines yield — the percentage of chips on a wafer that actually work.
"SMIC's 5nm wafers estimatedly cost 50% more than TSMC's equivalent in production, that too at yields reportedly as low as 33% — against TSMC's 80%+ in even comparison. And this, is not a minor efficiency gap. It represents structural manufacturing disadvantage that has potential to compound over every generation."
Resultantly, SMIC is producing chips at approximately 3,000–4,000 wafer starts per month at its 7nm-class process — sufficient for supplying Huawei's premium smartphones and AI accelerator business. But that's nowhere near being competitive at a commercial scale. On the other hand, TSMC produces roughly 100,000–120,000 wafer starts per month for Apple's A-series chips at 3nm. The volume gap is approximately 30 times.
For a specific customer, within a controlled supply-chain environment, SMIC's process works fine. But as a foundry business, competing in the open market for high-volume customers, the cost and yield disadvantage is strongly prohibitive.
The EUV Barrier — And Potential Loophole Around It
By convention, the semiconductor containment strategy is straightforward: deny Chinese access to EUV, deny them sub-10nm process, and maintain the technology gap indefinitely. This understanding is correct in principle, but dangerously incomplete in practice.
In 2024 alone, Chinese entities acquired approximately 90 of ASML's most advanced DUV immersion machines — the NXT:1980Fi series — representing 70% of ASML's global DUVi sales that year, worth an estimated $5–7 billion. These machines lie in a regulatory grey zone. They are not EUV. Thus, not technically covered by most export control thresholds. But... they are capable ones. Through multi-patterning, they can produce near-frontier chips at scale.
An April 2026 report by the American Enterprise Institute identified this as a structural loophole within the US semiconductor policy: the controls are marked at specific technical thresholds that make the NXT:1980Fi drop just outside the line.
This indicates that China's DUV acquisition is not incidental. It is deliberate. And the Chinese fabs appear to be stockpiling machine capacity before further restrictions close that window.
In turn, the Chinese strategy looks like building the manufacturing infrastructure at scale, and run multi-patterning processes at volumes to make the yield disadvantage commercially manageable through sheer throughput only.
Why This Is an Engineering Problem?
The framing of semiconductor competition in the form of sanctions and export controls misses the deeper reality: TSMC's advantage is not merely legal or geopolitical. It is also about the accumulated result of three decades of process engineering at an intensity and scale that is genuinely difficult to replicate.
Consider what ASML's EUV machines actually require to function.
The light source generates extreme ultraviolet radiation by firing lasers at 50,000 tin droplets per second. The optical system uses precise multilayer mirrors — manufactured by Zeiss (Germany) — with surface roughness measured in picometres. For idea: a single human hair contains millions of times more material than the tolerance margin in these mirrors. Hence, the entire machine operates as a system in which every component performs simultaneously at the cutting-edge of physical possibility. ASML took 30 years and approximately $8 billion in research and development to reach the current EUV capability. The knowledge embedded within that machine is not lying in any blueprint that China could just acquire.
The same principle applies to TSMC's process knowledge.
Semiconductor manufacturing is a discipline of yield improvement as the primary measure of engineering progress. Maturing a process from 40% yield to 80% at a given node requires thousands of small, accumulated insights about contamination sources, thermal management, material interactions, and equipment calibration. And this knowledge lives in the people, the documentation, the institutional memory, and the continuous experimentation cycles of a world-class manufacturing organisation. It cannot be just purchased and replicated. It cannot be forced into existence. And it does not transfer easily without building the founding substrate of understanding.
SMIC is capable and improving. Its engineers solved a genuinely hard problem in manufacturing 7nm without EUV. But the gap between "acquiring a node via an alternative route at low yield" and "manufacturing at commercial scale with competitive yield" is measured not in years but in engineering generations. And each generation requires the previous one to have fully understood the arena.
Where China Is Actually Winning?
A complete analysis requires acknowledging where China's semiconductor trajectory is genuinely formidable — and where Western complacency is at a greater risk.
In memory chips, the picture is substantially different from common logic. YMTC has captured approximately 18% of the global NAND market. CXMT is closing the gap in DRAM. Given the scenario, these are not trivial achievements. Memory chip production is less lithography-constrained than logic chips. Which means that the EUV ban is a smaller impediment. Hence, China's memory players are building real capability and capturing real market share at a rate that is faster than most Western industry analysis has acknowledged.
In chip design, Huawei's HiSilicon division has demonstrated that Chinese design capability — before being cut off from TSMC manufacturing and ARM licences — is genuinely world-class. The question of what Huawei's designers can produce when manufacturing constraints are removed is not trivial. Their design talent exists. Their manufacturing capability remains the limiting constraint.
In mature nodes — 28nm and above — China is no longer catching up. It has already arrived. Chinese foundry capacity of 28nm and legacy nodes is already sufficient to dominate the global market for automotive industry, industrial controllers, communications equipment, and a wide range of defence applications. This is strategically far more important than the most coverage suggests. Chips that control weapons, navigation equipment, aircraft subsystems, and military communications are not all manufactured at 3nm. They are mostly manufactured at nodes where China now has established and growing capability.
What This Means for Nations, Institutions, and Engineers
The gap between China and TSMC is real, substantial, and in the domain of leading-edge logic, is likely to persist for a decade or more. Taiwan's National Science Council estimates the gap at over ten years given the TSMC's 2nm production capability. The ASML CEO cited ten to fifteen years for the same. These are not propaganda figures — they reflect the compounding nature of process engineering advantage.
But the strategic implications depend critically on which domain one is analysing. For AI training, TSMC's advantage is decisive and SMIC cannot compete at scale. For defence electronics, mature nodes, and memory, China's position is substantially stronger and improving faster than the headlines like "China can't catch TSMC" suggest.
For those outside the US-China-Taiwan triangle, the race presents a clarifying question: which supply chains are you actually dependent on, and what happens to your industrial and defence capabilities if any supply chain is disrupted? Those, building their electronics ecosystems on TSMC-fabbed components face a different risk profile from those who — by choice or necessity — rely on Chinese-manufactured chips at mature nodes. Neither position is inherently stable.
"The chips that power weapons systems, aircraft avionics, and military communications are not all manufactured at 3nm. They are built at processes where China has already arrived. This is the dimension of the semiconductor race that deserves far more attention than it currently receives."
The Conclusion
China cannot catch TSMC at the cutting edge in the foreseeable future. It's a defensible statement. But it is also, at the same time, strategically misleading.
China does not need to catch TSMC to achieve its prime objectives. It needs to manufacture enough advanced chips to power its AI ecosystem, enough mature-nodes to equip its military, and enough domestic capability to reduce its vulnerability to supply chain disruptions. And on those objectives — not on competing with TSMC for Apple's business — China is making faster progress than the dominant narrative suggests.
Yes, the gap is real.
Yet the gap is being actively worked around — funded at a scale that simply dwarfs any comparable national industrial programme in history, and staffed by engineers who have demonstrated that they can solve problems that the rest of the world had assumed unsolvable.
Underestimating that is a strategic mistake. So is overestimating.
Comments
Post a Comment